1. Technical Field
Exemplary embodiments are directed to a method of manufacturing a semiconductor device, and more particularly to a method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process.
2. Discussion of the Related Art
In manufacturing a high density semiconductor device, a double patterning technology (DPT) process is generally used to avoid conflicts between patterns included in a layout of the semiconductor device. In a DPT process, a layout of a semiconductor device is decomposed into two patterns, and a wiring pattern is formed on a substrate by performing a lithography process on the substrate twice using the two patterns. A double pattern decomposition tool, which decomposes a layout of a semiconductor device into two patterns using a double pattern dividing algorithm, is generally used for a DPT process.
However, as a density of a semiconductor device further increases, it becomes challenging to meet a design rule using a DPT process. For this reason, a quadruple patterning technology (QPT) process, in which a layout of a semiconductor device is decomposed into four patterns, and four lithography processes are performed on the substrate using the four patterns to form the wiring pattern, has been developed.
However, it takes more time to decompose a layout of a semiconductor device into four patterns for a QPT process.